The present invention relates to techniques for trimming drive current in output drivers, and more particularly, to techniques for trimming drive current in output drivers to compensate for process variations and other abnormalities.
Integrated circuits (ICs) typically contain output drivers that drive output signals from inside the chip to an external terminal for transmission off-chip. An output driver has at least one pull-up transistor and at least one pull-down transistor. These transistors are used to drive digital signals to an external terminal (also called a pad).
The channel width-to-length (W/L) ratios (i.e., sizes) of the pull-up and pull-down transistors are typically chosen to meet a specific input/output (I/O) standard. Examples of I/O standards are LVTTL, LVCMOS, HSTL, GTL, and LVDS. Some integrated circuits support multiple version of an I/O standard for different supply voltages. For example, some ICs support 1.8 volt, 2.5 volt, and 3.3 volt standards for LVTTL I/Os.
In application specific integrated circuits (ASICs), the pull-up and pull-down transistors in the output drivers are a fixed size. In programmable logic integrated circuits, a customer can select from a variety of I/O standards. The programmable logic IC can be configured to connect appropriately sized output driver transistors to an I/O pad to meet the requirements of a selected I/O standard.
Circuit simulations are used to determine the transistor dimensions required to meet an I/O standard. However, the actual drive current of the pull-up and pull-down transistors in output drivers can differ significantly from design targets, because device models often contain inaccuracies, and the wafer fabrication process varies. Variations in output drive currents occur across a single die, as well as from die-to-die.
For a well-controlled process, the variation in drive current can be +/−10% and the nominal drive current may be 3% off target. For a poorly controlled process, the variation in drive current from a target value can be significantly larger. The process variation and the deviation of the process median from target are accounted for in the design process by running corner simulations that predict the behavior of devices and circuits across the expected worst-case range of outcomes from the wafer fabrication process.
The goal of prior art techniques is to ensure by design that the I/O drivers operate correctly within normal process variations. Designing an I/O driver that operates correctly within larger process variations typically involves some compromises that may reduce the performance or increase the area of the I/O driver. For example, the maximum speed of an I/O driver may be limited to ensure that requirements are met for the slowest corner of the process.
Variations in I/O characteristics cause system designers to build margin into a system so that it works correctly with the worst possible process variation. High speed I/O drivers, in particular, must have a well controlled output impedance to match the impedance of the transmission line and/or the receiver being driven. However, building margin into a system may degrade the performance or increase the cost of the system.
Inaccuracies in the models as well as drift in the process can cause the model prediction of a typical output drive current to deviate from the actual drive current observed on silicon. With the prior art approach, the only way to adjust the typical output drive current to match a target is to change a mask to modify the output transistor geometry or to change the process to put the output drive current on target.
Therefore, it would be desirable to provide techniques for adjusting the drive current of output drivers to compensate for process variations, model inaccuracies, and other abnormalities that do not require changes to a mask or the process.